 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 1 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 EM73461 4-bit micro-controller for lcd product general description EM73461 is an advanced single chip cmos 4-bit micro-controller. it contains 4k-byte rom, 244-nibble ram, 4-bit alu, 13-level subrountine nesting, 22-stage time base, two 12-bit timer/counters for the kernel function. EM73461 also contains 6 interrupt sources, 1 input port, 2 bidirection ports, lcd display (32x4), and one high speed timer/counter with melody output. EM73461 has plentiful operating modes (slow, idle, stop) intended to reduce the power consumption. features ? operation voltage : 1.2v ~ 1.8v and 2.4v to 3.6v. ? clock source : dual clock system. low-frequency oscillator is crystal or rc oscillator (32k hz, connect an external resistor) by mask option and high-frequency oscillator is rc oscillator (connect an external capacitor). ? instruction set : 109 powerful instructions. ? instruction cycle time : up to 2us for 4 mhz (high speed clock). up to 244 m s for 32768 hz (low speed clock). ? rom capacity : 4096 x 8 bits. ? ram capacity : 244 x 4 bits. ? input port : 1 port (p0). p0(0..3) and idle releasing function are available by mask option. ? bidirection port : 2 ports (p4, p8). p4.0 and sound is available by mask option. p4.1 is shared with htc external input. p8(0..3) and idle releasing function are available by mask option. ? 12-bit timer/counter : two 12-bit timer/counters are programmable for timer, event counter and pulse width measurement. ? high speed timer/counter : one 8-bit high speed timer/counters is programmable for auto load timer, melody output and pulse width measurement. ? built-in time base counter : 22 stages. ? subrountine nesting : up to 13 levels. ? interrupt : external . . . . . 2 input interrupt sources. internal . . . . . . 2 timer overflow interrupts, 1 time base interrupt. 1 high speed timer overflow interrupt. ? lcd driver : 32 x 4 dots, 1/4,1/3,1/2 static six kinds of duty selectable, 1/2 bias, 1/3 bias. ? power saving function :slow, idle, stop operation mode. ? package type : chip form 62 pins. applications EM73461 is suitable for application in family applicance, consumer products, hand held games and the toy controller.
2 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 function block diagram symbol pin-type function v dd power supply (+) v ss power supply (-) reset reset-a system reset input signal, low active mask option : none pull-up rcin osc-d rc clock source connecting pin rcout osc-d rc clock source connecting pin lxin osc-b/osc-f crstal/rc connecting pin for low speed clock source lxout osc-b/osc-f crstal/rc connecting pin for low speed clock source p0(0..3)/wakeup0..3 input-k 4-bit input port with idle releasing function mask option : wakeup enable, negative edge release, pull-up wakeup enable, negative edge release, none wakeup enable, positive edge release, pull-down wakeup enable, positive edge release, none wakeup disable, pull-up wakeup disable, pull-down wakeup disable, none p4.0/sound i/o-r 1-bit bidirection i/o port or inverse sound effect output mask option : sound enable, high current push-pull sound disable, open-drain pin descriptions interrupt control time base timer/counter (ta,tb) system control instruction decoder instruction register rom pc data bus reset control clock generator clock generator (slow) timing generator clock mode control data pointer acc alu flag zc s g stack pointer stack ram hr lr i/o control p0.0/wakeup0 p0.1/wakeup1 p0.2/wakeup2 p0.3/wakeup3 p4.0/sound p4.1/trgh p4.2 p4.3 p8.0(int1)/wakeupa p8.1(trgb)/wakeupb p8.2(int0)/wakeupc p8.3(trga)/wakeupd reset rcout lxin lxout htc lcd v2 v3 va vb v1 com0~com3 sound seg0~seg31 rcin 3 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 symbol pin-type function sound disable, low current push-pull sound disable, normal current push-pull sound disable, high current push-pull p4.1/trgh i/o-q 1-bit bidirection i/o port with htc external input mask option : nmos open-drain pmos open-drain low current push-pull normal current push-pull high current push-pull p4(2,3) i/o-q 2-bit bidirection i/o port with high current source mask option : nmos open-drain pmos open-drain low current push-pull normal current push-pull high current push-pull p8.0(int1)/wakeupa, i/o-s 2-bit bidirection i/o port with external interrupt source input and idle p8.2(int0)/wakeupc releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull p8.1(trgb)/wakeupb i/o-s 2-bit bidirection i/o port with time/counter a,b external input and idle p8.3(trga)/wakeupd releasing function mask option : wakeup enable, low current push-pull wakeup enable, normal current push-pull wakeup disable, open-drain wakeup disable, low current push-pull wakeup disable, normal current push-pull sound melody output va,vb, v1, v2, v3 connect the capacitors for lcd bias voltage com0~com3 lcd common output pins seg0~seg31 lcd segment output pins test test pin must be connected to v ss pin descriptions function descriptions program rom (4k x 8 bits) 4 k x 8 bits program rom contains users program and some fixed data . the basic structure of program rom can be divided into 5 parts. 1. address 000h: reset start address. 2. address 002h - 00ch: 6 kinds of interrupt service routine entry addresses . 3. address 00eh-086h : scall subroutine entry address, only available at 00eh,016h,01eh,026h, 02eh, 036h, 03eh, 046h, 04eh, 056h, 05eh, 066h, 06eh, 076h, 07eh, 086h . 4. address 000h - 7ffh : lcall subroutine entry address 5. address 000h - fffh : except used as above function, the other region can be used as users program region. 4 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 address 4096 x 8 bits 000h reset start address 002h int0; external interrupt service routine entry address 004h htci; high speed timer interrupt service entry address 006h trga; timer/countera interrupt service routine entry address 008h trgb; timer/counter b interrupt service routine entry address 00ah tbi; time base interrupt service routine entry address 00ch int1; external interrupt service routine entry address 00eh 086h fffh users program and fixed data are stored in the program rom. users program is according the pc value to send next executed instruction code . fixed data can be read out by two ways. (1) table-look-up instruction : table -look-up instruction is depended on the data pointer (dp) to indicate to rom address, then to get the rom code data. ldax acc ? rom[dp] l ldaxi acc ? rom[dp] h ,dp+1 dp is a 12-bit data register which can store the program rom address to be the pointer for the rom code . . . . . . scall, subroutine call entry address data. first, user load rom address into dp by instruction "ldadpl, ldadpm, ldadph", then user can get the lower nibble of rom code data by instruction "ldax" and higher nibble by instruction "ldaxi" program example: read out the rom code of address 777h by table-look-up instruction. ldia #07h; stadpl ; dp3-0 ? 07h stadpm ; dp5-4 ? 07h stadph ; dp8-6 ? 07h, load dp=777h : ldl #00h; ldh #03h; ldax ; acc ? 6h stami ; ram[30] ? 6h ldaxi ; acc ? 5h stam ; ram[31] ? 5h ; org 777h data 56h; : data ram ( 244-nibble ) there is total 244 - nibble data ram from address 00 to f3h data ram includes 3 parts: zero page region, stacks and data area. 5 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 lcd display ram: ram address from 20h ~ 3fh are the lcd display ram area, the ram data of this region can't be operated by instruction ldhl xx and exhl. zero- page: from 00h to 0fh is the location of zero-page . it is used as the pointer in zero -page addressing mode for the instruction of "std #k,y; add #k,y; clr y,b; cmp y,b". program example: to wirte immediate data "07h" to address "03h" of ram and to clear bit 2 of ram. std #07h, 03h ; ram[03] ? 07h clr 0eh,2 ; ram[0eh] 2 ? 0 stack: there are 13 - level ( maximum ) stack for user using for subroutine ( including interrupt and call). user can assign any level be the starting stack by giving the level number to stack pointer( sp) . when user using any instruction of call or subroutine, before entry the subroutine, the previous pc address will be saved into stack until return from those subroutines ,the pc value will be restored by the data saved in stack. data area: except the special area used by user, the whole ram can be used as data area for storing and loading general data. addressing mode (1) indirect addressing mode: indirect addressing mode indicates the ram address by specified hl register . for example: ldam ; acc ? ram[hl] stam ; ram[hl] ? acc (2) direct addressing mode: direct addressing mode indicates the ram address by immediate data . level 0 level 4 level 8 level c level 1 level 5 level 9 level 2 level 6 level a level 3 level17 level b b0h ~ bfh c0h ~ cfh d0h ~ dfh e0h ~ efh f0h ~ f3h address 00h~0fh 10h~1fh 20h~2fh 30h~3fh 40h~4fh : zero page lcd display ram increment 6 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 program counter (4k rom) program counter ( pc ) is composed by a 12-bit counter, which indicates the next executed address for the instruction of program rom. for a 4k - byte size rom, pc can indicate address form 000h - fffh, for branch and call instrcutions, pc is changed by instruction indicating. (1) branch instruction: sbr a object code: 00aa aaaa condition: sf=1; pc ? pc 11-6.a ( branch condition satisified ) pc hold original pc value+1 aaaaaa sf=0; pc ? pc +1( branch condition not satisified) pc original pc value + 1 lbr a object code: 1100 aaaa aaaa aaaa condition: sf=1; pc ? a ( branch condition satisified) pcaaaaaaaaaaaa sf=0 ; pc ? pc + 2 ( branch condition not satisified ) pc original pc value + 2 (2) subrountine instruction: scall a object code: 1110 nnnn condition : pc ? a ; a=8n+6 ; n=1..15 ; a=86h, n=0 pc0000 aaaaaaaa lcall a object code: 0100 0 aaa aaaa aaaa condition: pc ? a for example: lda x ; acc ? ram[x] sta x ; ram[x] ? acc (3) zero-page addressing mode for zero-page region, user can using direct addressing to write or do any arithematic, comparsion or bit manupulated operation directly. for example: std #k,y ; ram[y] ? #k add #k,y; ram[y] ? ram[y] + #k pc0aaaaaaaaaaa 7 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 accumulator ret object code: 0100 1111 condition: pc ? stack[sp]; sp + 1 pc the return address stored in stack rt i object code: 0100 1101 condition : flag. pc ? stack[sp]; ei ? 1; sp + 1 pc the return address stored in stack (3) interrupt acceptance operation: when an interrupt is accepted, the original pc is pushed into stack and interrupt vector will be loaded into pc,the interrupt vectors are as following: int0 (external interrupt from p8.2) pc000000000010 trga (timer a overflow interrupt) pc000000000110 trgb (time b overflow interrupt) pc000000001000 tbi (time base interrupt) pc000000001010 int1 (external interrupt from p8.0) pc000000001100 (4) reset operation: pc000000000000 (5) other operations: for 1-byte instruction execution: pc + 1 for 2-byte instruction execution: pc + 2 8 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 there are four kinds of flag, cf ( carry flag ), zf ( zero flag ), sf ( status flag ) and gf ( general flag ), these 4 1-bit flags are affected by the arithematic, logic and comparative .... operation . all flags will be put into stack when an interrupt subrountine is served, and the flags will be restored after rti instruction executed . (1) carry flag ( cf ) the carry flag is affected by following operation: a. addition : cf as a carry out indicator, when the addition operation has a carry-out, cf will be "1", in another word, if the operation has no carry-out, cf will be "0". b. subtraction : cf as a borrow-in indicator, when the subtraction operation must has a borrow, in the cf will be "0", in another word, if no borrow-in, cf will be "1". c. comparision: cf is as a borrow-in indicator for comparision operation as the same as subtraction operation. d. rotation: cf shifts into the empty bit of accumulator for the rotation and holds the shift out data after rotation. e. cf test instruction : for tfcfc instruction, the content of cf sends into sf then clear itself "0". for ttsfc instruction, the content of cf sends into sf then set itself "1". (2) zero flag ( zf ) zf is affected by the result of alu, if the alu operation generate a "0" result, the zf will be "1", otherwise, the zf will be "0". (3) status flag ( sf ) the sf is affected by instruction operation and system status . a. sf is initiated to "1" for reset condition . b. branch instruction is decided by sf, when sf=1, branch condition will be satisified, otherwise, branch condition will not be satisified by sf = 0 . (4) general flag ( gf ) gf is a one bit general purpose register which can be set, clear, test by instruction sgf, cgf and tgs. program example: check following arithematic operation for cf, zf, sf accumulator is a 4-bit data register for temporary data . for the arithematic, logic and comparative opertion .., acc plays a role which holds the source data and result . flags 9 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 cf zf sf ldia #00h; - 1 1 ldia #03h; - 0 1 adda #05h; - 0 1 adda #0dh; - 0 0 adda #0eh; - 0 0 alu the arithematic operation of 4 - bit data is performed in alu unit. there are 2 flags can be affected by the result of alu operation, zf and sf . the operation of alu can be affected by cf only . alu structure alu supported user arithematic operation function, including : addition, subtraction and rotaion. alu function (1) addition: for instruction addam, adcam, addm #k, add #k,y .... alu supports addition function. the addition operation can affect cf and zf. for addition operation, if the result is "0", zf will be "1", otherwise, not equal "0", zf will be "0", when the addition operation has a carry-out. cf will be "1", otherwise, cf will be "0". example: operation carry zero 3+4=7 0 0 7+f=6 1 0 0+0=0 0 1 8+8=0 1 1 (2) subtraction: for instruction subm #k, suba #k, sbcam, decm... alu supports user subtraction function . the subtraction operation can affect cf and zf, for subtraction operation, if the result is negative, cf will be "0", it means a borrow out, otherwise, if the result is positive, cf will be "1". for zf, if the result of subtraction operation is "0", the zf will be "1", otherwise, zf will be "1". zf cf sf gf alu data bus 10 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 example: operation carry zero 8-4=4 1 0 7-f= -8(1000) 0 0 9-9=0 1 1 (3) rotation: there are two kinds of rotation operation, one is rotation left, the other is rotation right. rlca instruction rotates acc value to left, shift the cf value into the lsb bit of acc and the shift out data will be hold in cf. rrca instruction operation rotates acc value to right, shift the cf value into the msb bit of acc and the shift out data will be hold in cf. program example: to rotate acc right and shift a "1" into the msb bit of acc . ttcfs; cf ? 1 rrca; rotate acc right and shift cf=1 into msb. hl register hl register are two 4-bit registers, they are used as a pair of pointer for the address of ram memory and also 2 independent temporary 4-bit data registers. for some instruction, l register can be a pointer to indicate the pin number ( port4 ) . hl register structure hl register function acc cf msb lsb 3 2 1 0 h register 3 2 1 0 l register acc cf msb lsb 11 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 (1) for instruction : ldl #k, ldh #k, tha, thl, incl, decl, exal, exah, hl register used as a temporary register . program example: load immediate data "5h" into l register, "dh" into h register. ldl #05h; ldh #0dh; (2) for instruction ldam, stam, stami .., hl register used as a pointer for the address of ram memory. program example: store immediate data #ah into ram of address 35h. ldl #5h; ldh #3h; stdmi #0ah; ram[35] ? ah (3) for instruction : selp, clpl, tfpl, l regieter be a pointer to indicate the bit of i/o port. when lr = 0 indicate p4.0 program example: to set bit 0 of port4 to "1" ldl #00h; sepl ; p4.0 ? 1 stack pointer (sp) stack pointer is a 4-bit register which stores the present stack level number. before using stack, user must set the sp value first, cpu will not initiate the sp value after reset condition . when a new subroutine is accepted, the sp will be decreased one automatically, in another word, if returning from a subroutine, the sp will be increased one . the data transfer between acc and sp is by instruction of "ldasp" and "stasp". data pointer (dp) data pointer is a 12-bit register which stores the address of rom can indicate the rom code data specified by user (refer to data rom). clock and timing generator the clock generator is supported by a single clock system, the clock source comes from crystal (resonator) or rc oscillation is decided by mask option, the working frequency range is 480 k hz to 4 mhz depending on the working voltage. clock generator structure there are two clock generator for system clock control. p14 is the status register for the cpu status. p16, p19 and p22 are the system clock mode control ports. 12 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 system clock mode control the system clock mode controller can start or stop the high-frequency and low-frequency clock oscillator and switch between the basic clocks. EM73461 has four operation modes (normal, slow,idle and stop operation modes). operation mode oscillator system clock available function one instruction cycle normal high, low frequency high frequency clock lcd, high speed timer 8 / fc slow low frequency low frequency clock lcd, high speed timer 8 / fs idle low frequency cpu stops lcd - stop none cpu stops all disable - stop operation mode normal operation mode idle (cpu stops) slow operation mode reset operation high osc : stopped low osc : stopped high osc : stopped low osc : oscillating high osc : oscillating low osc : oscillating high osc : stopped low osc : oscillating command (p16) command (p16) command (p22) command (p22) command (p19) reset reset reset reset reset release i/o wakeup i/o or internal timer wakeup high-frequency generator system clock mode control fc rcin fs system control rc connection crystal connection lxin lxout p14 p16 p22 p19 low-frequency generator mask option for choose crystal or rc oscillator lxin lxout lxin lxout rcout 13 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 normal operation mode the 4-bit m c is in the normal operation mode when the cpu is reseted. this mode is a dual clock system (high-frequency and low-frequency clocks oscillating). it can be changed to slow or stop operation mode by the command register (p22 or p16). lcd display and high speed timer/counter with melody output are available for the normal operation mode. slow operation mode the slow operation mode is a single clock system (low-frequency clock oscillating). it can be changed to the dual operation mode with the commoand register (p22), stop operation mode with p16 and idle operation mode with p19. lcd display and high speed timer/counter with melody output are available for the slow operation mode. p22 32 1 0 initial value : 0000 * som som select operation mode 0 0 0 normal operation mode 1 * * slow operation mode p14 32 10 initial value : *000 * wks lfs cpus lfs low-frequency status cpus cpu status 0 lxin source is not stable 0 normal operation mode 1 lxin source is stable 1 slow operation mode wks wakeup status 0 wakeup not by internal timer 1 wakeup by internal timer port14 is the status register for cpu. p14.0 (cpu status) and p14.1 (low-frequency status) are read-only bits. p14.2 (wakeup status) will be set to '1' when cpu is wake-up by internal timer. p14.2 will be cleared to '0' when user out data to p14. idle operation mode the idle operation mode suspends all slow operations except for the low-frequency clock and lcd driver. it retains the internal status with low power consumption without stopping the clock function and lcd display. lcd display is available for the idle operation mode. sound generator is disabled in this mode. the idle operation mode will be wakeup and return to the slow operation mode by the internal timing generator or i/o pins (p0(0..3)/wakeup 0..3 or p8(0..3)/wakeupa..d). 14 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 time base interrupt (tbi ) the time base can be used to generate a fixed frequency interrupt . there are 8 kinds of frequencies can be selected by setting p25 p25 3 2 1 0 i nitial value : 0000 p25 normal operation mode slow operation mode 0 0 x x interrupt disable interrupt disable 0 1 0 0 interrupt frequency lxin / 2 3 hz reserved 0 1 0 1 interrupt frequency lxin / 2 4 hz reserved 0 1 1 0 interrupt frequency lxin / 2 5 hz reserved 0 1 1 1 interrupt frequency lxin / 2 14 hz interrupt frequency lxin / 2 14 hz 1 1 0 0 interrupt frequency lxin / 2 1 hz reserved 1 1 0 1 interrupt frequency lxin / 2 6 hz interrupt frequency lxin / 2 6 hz 1 1 1 0 interrupt frequency lxin / 2 8 hz interrupt frequency lxin / 2 8 hz 1 1 1 1 interrupt frequency lxin / 2 10 hz interrupt frequency lxin / 2 10 hz 1 0 x x reserved reserved timer / counter ( timera, timerb) timer/counters can support user three special functions: 1. even counter 2. timer. 3. pulse-width measurement. idme sidr idme enable idle mode sidr select idle releasing condition 0 1 enable idle mode 0 0 p0(0..3), p8(0..3) pin input * * reserved 0 1 p0(0..3), p8(0..3) pin input and 1 sec signal 1 0 p0(0..3), p8(0..3) pin input and 0.5 sec signal 1 1 p0(0..3), p8(0..3) pin input and 15.625 ms signal stop operation mode the stop operation mode suspends system operation and holds the internal status immediately before the suspension with low power consumption. this mode will be released by reset or i/o pins (p0(0..3)/ wakeup 0..3 or p8(0..3)/wakeup a..d). lcd display and high speed timer/counter with melody output are disabled in the mode. p16 3210 initial value : 0000 spme swwt spme enable stop mode swwt set wake-up warm-up time 0 1 enable stop mode 0 0 2 18 /rcin * * reserved 0 1 2 14/ rcin 10 2 16 /rcin 1 1 reserved p19 32 10 initial value : 0000 15 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 these three functions can be executed by 2 timer/counter independently. for timera, the counter data is saved in timer register tah, tam, tal, which user can set counter initial value and read the counter value by instruction "ldatah(m,l), statah(m,l)" and timer register is tbh, tbm, tbl and w/r instruction "ldatbh (m,l), statbh (m,l)". the basic structure of timer/counter is composed by two same structure counter, these two counters can be set initial value and send counter value to timer register, p28 and p29 are the command ports for timera and timer b, user can choose different operation mode and different internal clock rate by setting these two ports. when timer/counter overflow, it will generate a trga(b) interrupt request to interrupt control unit. interrupt control trga request p8.3/ trga event counter control timer control internal clock p28 12 bit counter tmsa ipsa data bus p8.1/ trgb event counter control timer control internal clock high speed timer/counter p29 12 bit counter mux tmsb ipsb trgb request pulse-width measurement control pulse-width measurement control port 28 3 2 1 0 tmsa ipsa initial state: 0000 timer/counter mode selection tmsa (b) function description 0 0 stop 0 1 event counter mode 1 0 timer mode 1 1 pulse width measurement mode port 29 3 2 1 0 tmsb ipsb initial state: 0000 timer/counter control p8.1/trgb, p8.3/trga are the external timer inputs for timerb and timera, they are used in event counter and pulse-width measurement mode. timer/counter command port: p28 is the command port for timer/countera and p29 is for the timer/ counterb. internal pulse-rate selection internal pulse-rate selection ipsa normal mode slow mode ipsb normal mode slow mode 0 0 lxin/2 3 hz reserved 0 0 depend on high speed timer/counter 0 1 lxin/2 7 hz lxin/2 7 hz 0 1 lxin/2 5 hz lxin/2 5 hz 1 0 lxin/2 11 hz lxin/2 11 hz 1 0 lxin/2 9 hz lxin/2 9 hz 1 1 lxin/2 15 hz lxin/2 15 hz 1 1 lxin/2 13 hz lxin/2 13 hz 16 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 internal pulse timerb (timera )value n n+1 n+2 n+3 n+4 n+5 n+6 n+7 p8.1/trgb (p8.3/trga) timerb (timera) value n n+1 n+2 n+3 n+4 n+5 n+6 timer/counter function timer/countera can be programmable for timer, event counter and pulse width measurement. each timer/ counter can execute any one of these functions independly. event counter mode for event counter mode, timer/counter increases one at any rising edge of p8.1/trgb for timerb (p8.3/ trga for timer a). when timerb (timera) counts overflow, it will give interrupt control an interrupt request trgb (trga). program example: enable timera with p28 ldia #0100b; outa p28; enable timera with event counter mode timer mode for timer mode ,timer/counter increase one at any rising edge of internal pulse . user can choose 4 kinds of internal pulse rate by setting ipsb for timerb (ipsa for timera). when timer/counter counts overflow, trgb (trga) will be generated to interrupt control unit. program example: to generate trga interrupt request after 60 ms with system clock lxln=32khz ldia #0100b; exae; enable mask 2 eicil 110111b; interrupt latch ? 0, enable ei ldia #0ah; statal; ldia #00h; statam; ldia #0fh; statah; ldia #1000b; outa p28; enable timera with internal pulse rate: lxin/2 3 hz note: the preset value of timer/counter register is calculated as following procedure. internal pulse rate: lxin/2 3 ; lxin = 32khz the time of timer counter count one = 2 3 /lxin = 8/32768=0.244ms the number of internal pulse to get timer overflow = 60 ms/ 0.244ms = 245.901= 0f6h the preset value of timer/counter register = 1000h - 0f6h = 0f0ah pulse width measurement mode 17 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 for the pulse width measurement mode, the counter only incresed by the rising edge of internal pulse rate as external timer/counter input (p8.1/trgb, p8.3/trga ), interrupt request will be generated as soon as timer/counter count overflow. internal pulse timerb(timera) value n n+1 n+2 n+3 n+4 n+5 p8.1/trgb(p8.3/trga) program example: enable timera by pulse width measurement mode . ldia #1100b; outa p28; enable timera with pulse width measurement mode. high speed timer/counter EM73461 has one 8-bit high speed timer/counter (htc). it supports three special functions : auto load timer, melody output and pulse width measurement modes. the htc is available for the normal and slow operation mode. the htc can be set initial value and send counter value to counter registers (p11 and p10), p31 is the command port for htc, user can choose different operation mode and different internal clockrate by setting the port. the timer/counter increase one at the rising edge of internal pulse. the htc can generate an overflow interrupt (htci) when it overflows. the htci cannot be generated when the htc is in the melody mode or disabled. p31 is the command register of the 8-bit high speed timer/counter. p31 32 1 0 initial value : 0000 htms hips htms mode selection hips clock rate selection normal mode slow mode 0 0 stop 0 0 lxin/2 0 hz lxin/2 0 hz 0 1 auto load timer mode 0 1 lxin/2 2 hz lxin/2 2 hz 1 0 melody mode 1 0 rcin/2 4 hz reserved 1 1 pulse width measurement mode 1 1 rcin/2 6 hz reserved p31(3,2) p4.0/sound sound p4.1/trgh 8-bit binary counter p31(1,0) p11 ? p10 xin input data data bus reload overflow htci interrupt timer/counter b output data mask option f htc p11 and p10 are the counter registers of the 8-bit high speed timer/counter. p10 is the lower nibble register and p11 is the higher nibble register. (ht is the value of counter registers.) p11 32 1 0 p10 3210 initial value : 0000 0000 (ht) higher nibble register lower nibble register 18 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 ** f htc =[(xin/2 x )/(100h-ht)]/2, ht=0~255 ** example : lxin=32k hz, hips=01, ht=11110000b=0f0h. t f htc =[(32k hz/2 2 )/(100h-0f0h)]/2=256 hz. ldia #1111b outa p11 ldia #0000b outa p10 ldia #1001b outa p31 the value of 8-bit binary up counter can be presetted by p10 and p11. the value of registers can loaded into the htc when the counter starts counting or occurs overflow. if user write value to the registers before the next overflow occurs, the preset value can be changed. the preset value will be changed when users output the different data to p10 and p11. the count value of htc can be read from p10 and p11. the value is unstable when user read the value during counting. thus, user must disable the counter before reading the value. the p4.0/sound and sound pins will output the squre wave in the melody mode. when the cpu is not in the melody mode, the p4.0/sound is high and sound is low. the p4.1/rgh pin will be the input pin in the pulse width measurement mode. user must output high to p4.1/ trgh and then it can be the htc external input pin. when the htc is disabled, the p4.1 pin is a normal i/ o pin. interrupt function there are 6 interrupt sources, 2 external interrupt sources, 4 internal interrupt sources . multiple interrupts are admitted according the priority . type interrupt source priority interrupt interrupt program rom latch enable condition entry address external external interrupt(int0) 1 il5 ei=1 002h internal high speed timer overflow interrupt (htci) 2 il4 ei=1, mask3=1 004h internal timera overflow interrupt (trga) 3 il3 ei=1, mask2=1 006h internal timerb overflow interrupt (trgb) 4 il2 ei=1, mask1=1 008h internal time base interrupt(tbi) 5 il1 00ah external external interrupt(int1) 6 il0 ei=1,mask0=1 00ch interrupt structure reset by system reset and program instruction mask0 mask1 mask1 mask2 mask3 il0 int1 r0 il1 tbi r1 il2 r2 il3 trga r3 il4 r4 il5 int0 r5 priority checker ei entry address generator interrupt request interrupt entry address reset by system reset and program instruction set by program instruction trgb htci 19 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 lcd driver EM73461 can directly drive the liquid crystal display (lcd) and has 32 segment, 4 common output pins (1/ 2 bias, 1/3 bias). there are total 32x4 dots can be display. the v1, v2, v3, va, vb, vdd and vss pins are the lcd bias generator. control of lcd driver the lcd driver control command register is p27. when ldc is 0, the lcd is disabled, the com and seg pins are vss. when ldc is 1, the lcd driver enables. when the cpu is reseted or during the stop operation mode, the lcd driver is disabled. port27 3 2 1 0 initial value : 0000 ldc duty ldc lcd display control duty driving method select 0 lcd display disable 0 0 0 1/4 duty (1/3 bias) 1 lcd display enable 0 0 1 1/4 duty (1/2 bias) 0 1 0 1/3 duty (1/3 bias) 0 1 1 1/3 duty (1/2 bias) 1 0 0 1/2 duty (1/2 bias) 1 0 1 static 1 1 * reserved the lcd display data is stored in the display data area of the data memory (ram). the display data area begins with address 20h during reset. the lcd display data area ia as below : interrupt controller: il0-il5 : interrupt latch . hold all interrupt requests from all interrupt sources. ilr can not be set by program, but can be reset by program or system reset, so il only can decide which interrupt source can be accepted. mask0-mask3 : except int0 ,mask register can promit or inhibit all interrupt sources. ei : enable interrupt flip-flop can promit or inhibit all interrupt sources, when inter- rupt happened, ei is cleared to "0" automatically, after rti instruction happened, ei will be set to "1" again . priority checker: check interrupt priority when multiple interrupts happened. interrupt function the procedure of interrupt operation: 1. push pc and all flags to stack. 2. set interrupt entry address into pc. 3. set sf= 1. 4. clear ei to inhibit other interrupts happened. 5. clear the il for which interrupt source has already be accepted. 6. to excute interrupt subrountine from the interrupt entry address. 7. cpu accept rti, restore pc and flags from stack . set ei to accept other interrupt requests. program example: to enable interrupt of "int0, trga" ldia #1100b; exae; set mask register "1100b" eicil 111111b ; enable interrupt f.f. 20 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 ram com3 com2 com1 com0 address bit3 bit2 bit1 bit0 seg0 20h seg1 21h seg2 22h :: :: seg30 3eh seg31 3fh the relation between lcd display data and driving method driving method bit3 bit2 bit1 bit0 1/4 duty com3 com2 com1 com0 1/3 duty - com2 com1 com0 1/2 duty - - com1 com0 static - - - com0 lcd frame frequency : according to the drive method to set the frame frequency. duty frame frequency (hz) 1/4 duty 64 x (4/4) = 64 1/3 duty 64 x (4/3) = 85 1/2 duty 64 x (4/2) = 128 static 64 v dd v3 v2 v1 v ss 3v 2v 1v va vb v dd v3 v2 v1 v ss 4.5v 3v 1.5v va vb v dd v3 v2 v1 v ss 3v 2v 1v va vb v dd v3 v2 v1 v ss 4.5v 3v 1.5v va vb v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss -v1 -v2 -v3 v3 v2 v1 vss -v1 -v2 -v3 frame v3 v2 v1 vss v3 v2 v1 vss -v1 -v2 -v3 v3 v2 v1 vss -v1 -v2 -v3 frame com0 com1 com2 com3 seg0 seg0-com0 on seg0-com1 off (1) 1/4 duty (1/3 bias) (2 ) 1/3 duty (1/3 bias) ? vdd=3v lcd driving methods there are six kinds of driving methods can be selected by duty (p27.0~p27.2). the drivinf waveforms of lcd driver are as below : program example : ldia #0001b ; 1/4 duty, 1/2 bias outa p27 ldia #1001b ; enable lcd outa p27 21 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 v dd v3 v2 v1 v ss 3v 1.5v va vb v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame com0 com1 com2 com3 seg0 seg0-com0 on seg0-com1 off v dd v3 v2 v1 v ss 3v 1.5v va vb v dd v3 v2 v1 v ss 3v 1.5v va vb v dd v3 v2 v1 v ss 3v 1.5v va vb v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame v3 vss v3 v1 vss v3 vss -v3 vss -v3 frame v3 (6) static (5) 1/2 duty (1/2 bias) (4) 1/3 duty (1/2 bias) (3) 1/4 duty (1/2 bias) on off v dd v3 v2 v1 v ss va vb 4.5v v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss v3 v2 v1 vss -v1 -v2 -v3 v3 v2 v1 vss -v1 -v2 -v3 frame v3 v2 v1 vss v3 v2 v1 vss -v1 -v2 -v3 v3 v2 v1 vss -v1 -v2 -v3 frame com0 com1 com2 com3 seg0 seg0-com0 on seg0-com1 off (1) 1/4 duty (1/3 bias) (2 ) 1/3 duty (1/3 bias) 1.5v 3v v dd v3 v2 v1 v ss va vb 4.5v 1.5v 3v ? vdd=1.5v 22 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 v dd v3 v2 v1 v ss 3v va vb v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame com0 com1 com2 com3 seg0 seg0-com0 on seg0-com1 off v dd v3 v2 v1 v ss 3v 1.5v va vb v dd v3 v2 v1 v ss 3v 1.5v va vb v dd v3 v2 v1 v ss 3v 1.5v va vb v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame v3 v1 vss v3 v1 vss v3 v1 vss v3 v1 vss -v1 -v3 v3 v1 vss -v1 -v3 frame v3 vss v3 v1 vss v3 vss -v3 vss -v3 frame v3 (6) static (5) 1/2 duty (1/2 bias) (4) 1/3 duty (1/2 bias) (3) 1/4 duty (1/2 bias) on off 1.5v resetting function when cpu in normal working condition and reset pin holds in low level for three instruction cycles at least, then cpu begins to initialize the whole internal states, and when reset pin changes to high level, cpu begins to work in normal condition. the cpu internal state during reset condition is as following table : hardware condition in reset state initial value program counter 0000h status flag 01h interrupt enable flip-flop ( ei ) 00h mask0 ,1, 2, 3 00h interrupt latch ( il ) 00h p10, 11,14, 16, 19, 25, 27, 28, 29, 31 00h p4, 8, 23, 24 0fh both oscillator start oscillation the reset pin is a hysteresis input pin and it has a pull-up resistor available by mask option. the simplest reset circuit is connect reset pin with a capacitor to v ss and a diode to v dd . reset 23 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 EM73461 i/o port description : port input function output function note 0 e input port , wakeup function 1-- -- 2-- -- 3-- -- 4 e input port e output port, p4.0/sound 5-- -- 6-- -- 7-- -- 8 e input port, wakeup function, e output port 9-- -- 10 -- i high speed timer/counter low nibble 11 -- i high speed timer/counter high nibble 12 -- -- 13 -- -- 14 i cpu status i clear p14.0 to 0 15 -- -- 16 i stop mode control register 17 -- 18 -- 19 i idle mode control register 20 -- 21 -- 22 i slow mode control register 23 -- 24 -- 25 i timebase control register 26 -- 27 i lcd control register 28 i timer/counter a control register 29 i timer/counter b control register 30 -- 31 i htc control register 24 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 absolute maximum ratings items sym. ratings conditions supply voltage v dd -0.5v to 6v input voltage v in -0.5v to v dd +0.5v output voltage v o -0.5v to v dd +0.5v power dissipation p d 300mw t opr =50 c operating temperature t opr 0 c to 50 c storage temperature t stg -55 c to 125 c recommanded operating conditions items sym. ratings condition supply voltage v dd 1.2v to 1.8v 100khz 26 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 reset pin type type reset-a i/o pin type type i/o-n type i/o-q reset mask option lxin lxout crystal osc. rcin rcout rc osc. (inverter) : mask option wakeup mask option positive edge detector negative edge detector input data : mask option : mask option lxin lxout rc osc. (inverter) input pin type type input-k type osc-f oscillation pin type type osc-b type osc-d 27 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 type i/o-r type i/o-s path a : for set and clear bit of port instructions, data goes through path a from output data latch to cpu. path b : for input and test instructions, data from output pin go through path b to cpu and the output data latch will be set to high. input data output data path b path a type i/o-q output data latch special function output : mask option type i/o-n output data latch input data output data path b path a sel special function control input wakeup function mask option 28 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 pad diagram unit : m m chip size : 2160 x 2370 m m note : for pcb layout, ic substrate must be floated or connected to v ss . 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 (0,0) EM73461 vss rcin rcout lxout lxin vdd p4.3 p4.2 p4.1/trgh p4.0/sound sound p8.3 p8.2 p8.1 p8.0 reset seg6 seg7 seg8 seg9 seg10 seg11 seg13 seg14 seg15 seg16 seg17 seg18 seg19 seg20 seg12 seg21 seg0 v1 v2 v3 va vb com1 com2 com3 seg1 seg2 seg3 seg4 seg5 com0 test p0.3 p0.2 p0.1 p0.0 seg31 seg30 seg29 seg28 seg27 seg26 seg25 seg24 seg23 seg22 pad no. symbol x y 1 vss -1153.6 1271.6 2 rcin -1172.7 1103.8 3 rcout -1172.7 951.2 4 lxout -1172.7 798.6 5 lxin -1172.7 646.0 6 vdd -1151.5 492.7 7 p4.3 -1172.7 248.5 8 p4.2 -1172.7 70.9 9 p4.1/trgh -1172.7 -103.8 10 p4.0/sound -1172.7 -281.5 11 sound -1171.6 -454.9 12 p8.3 -1172.7 -617.2 13 p8.2 -1172.7 -769.8 14 p8.1 -1172.7 -926.3 15 p8.0 -1172.7 -1078.9 16 reset -1172.7 -1234.1 17 test -970.7 -1306.3 18 p0.3 -812.1 -1306.3 19 p0.2 -659.5 -1306.3 29 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 pad no. symbol x y 20 p0.1 -496.3 -1306.3 21 p0.0 -343.7 -1306.3 22 seg31 -185.7 -1306.3 23 seg30 -33.1 -1306.3 24 seg29 119.5 -1306.3 25 seg28 272.1 -1306.3 26 seg27 424.7 -1306.3 27 seg26 577.3 -1306.3 28 seg25 729.9 -1306.3 29 seg24 882.5 -1306.3 30 seg23 1035.1 -1306.3 31 seg22 1187.7 -1306.3 32 seg21 1172.7 -1143.9 33 seg20 1172.7 -991.3 34 seg19 1172.7 -838.7 35 seg18 1172.7 -686.1 36 seg17 1172.7 -533.5 37 seg16 1172.7 -380.9 38 seg15 1172.7 -228.3 39 seg14 1172.7 -75.7 40 seg13 1172.7 76.9 41 seg12 1172.7 229.5 42 seg11 1172.7 382.1 43 seg10 1172.7 534.7 44 seg9 1172.7 687.3 45 seg8 1172.7 839.9 46 seg7 1172.7 992.5 47 seg6 1172.7 1145.1 48 seg5 1187.7 1307.5 49 seg4 1035.1 1307.5 50 seg3 882.5 1307.5 51 seg2 729.9 1307.5 52 seg1 577.3 1307.5 53 seg0 424.7 1307.5 54 com3 272.1 1307.5 55 com2 119.5 1307.5 56 com1 -33.1 1307.5 57 com0 -185.7 1307.5 58 vb -338.3 1307.5 59 va -490.9 1307.5 60 v3 -643.5 1307.5 61 v2 -796.1 1307.5 62 v1 -948.7 1307.5 30 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 instruction table (1) data transfer mnemonic object code ( binary ) operation description byte cycle flag cz s lda x 0110 1010 xxxx xxxx acc ? ram[x] 2 2 - z 1 ldam 0101 1010 acc ? ram[hl] 1 1 - z 1 ldax 0110 0101 acc ? rom[dp] l 12-z1 ldaxi 0110 0111 acc ? rom[dp] h ,dp+1 1 2 - z 1 ldh #k 1001 kkkk hr ? k11--1 ldhl x 0100 1110 xxxx xx00 lr ? ram[x],hr ? ram[x+1] 2 2 - - 1 ldia #k 1101 kkkk acc ? k11-z1 ldl #k 1000 kkkk lr ? k11--1 sta x 0110 1001 xxxx xxxx ram[x] ? acc 2 2 - - 1 stam 0101 1001 ram[hl] ? acc 1 1 - - 1 stamd 0111 1101 ram[hl] ? acc, lr-1 1 1 - z c stami 0111 1111 ram[hl] ? acc, lr+1 1 1 - z c' std #k,y 0100 1000 kkkk yyyy ram[y] ? k22--1 stdmi #k 1010 kkkk ram[hl] ? k, lr+1 1 1 - z c' tha 0111 0110 acc ? hr 1 1 - z 1 tla 0111 0100 acc ? lr 1 1 - z 1 (2) rotate mnemonic object code ( binary ) operation description byte cycle flag czs rlca 0101 0000 ? cf ? acc ? 11czc' rrca 0101 0001 ? cf ? acc ? 11czc' ( 3) arithmetic operation mnemonic object code ( binary ) operation description byte cycle flag c zs adcam 0111 0000 acc ? acc + ram[hl] + cf 1 1 c z c' add #k,y 0100 1001 kkkk yyyy ram[y] ? ram[y] +k 2 2 - z c' adda #k 0110 1110 0101 kkkk acc ? acc+k 2 2 - z c' addam 0111 0001 acc ? acc + ram[hl] 1 1 - z c' addh #k 0110 1110 1001 kkkk hr ? hr+k 2 2 - z c' addl #k 0110 1110 0001 kkkk lr ? lr+k 2 2 - z c' addm #k 0110 1110 1101 kkkk ram[hl] ? ram[hl] +k 2 2 - z c' deca 0101 1100 acc ? acc-1 1 1 - z c decl 0111 1100 lr ? lr-1 1 1 - z c decm 0101 1101 ram[hl] ? ram[hl] -1 1 1 - z c inca 0101 1110 acc ? acc + 1 1 1 - z c' 31 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 incl 0111 1110 lr ? lr + 1 1 1 - z c' incm 0101 1111 ram[hl] ? ram[hl]+1 1 1 - z c' suba #k 0110 1110 0111 kkkk acc ? k-acc 2 2 - z c sbcam 0111 0010 acc ? ram[hll - acc - cf' 1 1 c z c subm #k 0110 1110 1111 kkkk ram[hl] ? k - ram[hl] 2 2 - z c ( 4) logical operation mnemonic object code ( binary ) operation description byte cycle flag czs anda #k 0110 1110 0110 kkkk acc ? acc&k 2 2 - z z' andam 0111 1011 acc ? acc & ram[hl] 1 1 - z z' andm #k 0110 1110 1110 kkkk ram[hl] ? ram[hl]&k 2 2 - z z' ora #k 0110 1110 0100 kkkk acc ? acc k 2 2 - z z' oram 0111 1000 acc ? acc ram[hl] 1 1 - z z' orm #k 0110 1110 1100 kkkk ram[hl] ? ram[hl] k 2 2 - z z' xoram 0111 1001 acc ? acc^ram[hl] 1 1 - z z' (5) exchange mnemonic object code ( binary ) operation description byte cycle flag czs exa x 0110 1000 xxxx xxxx acc ? ram[x] 2 2 - z 1 exah 0110 0110 acc ? hr 1 2 - z 1 exal 0110 0100 acc ? lr 1 2 - z 1 exam 0101 1000 acc ? ram[hl] 1 1 - z 1 exhl x 0100 1100 xxxx xx00 lr ? ram[x], hr ? ram[x+1] 2 2 - - 1 (6) branch mnemonic object code ( binary ) operation description byte cycle flag czs sbr a 00aa aaaa if sf=1 then pc ? pc 11-6 .a 5-0 11--1 else null lbr a 1100 aaaa aaaa aaaa if sf= 1 then pc ? a else null 2 2 - - 1 (7) compare mnemonic object code ( binary ) operation description byte cycle flag czs cmp #k,y 0100 1011 kkkk yyyy k-ram[y] 2 2 c z z' cmpa x 0110 1011 xxxx xxxx ram[x]-acc 2 2 c z z' cmpam 0111 0011 ram[hl] - acc 1 1 c z z' cmph #k 0110 1110 1011 kkkk k - hr 2 2 - z c cmpia #k 1011 kkkk k - acc 1 1 c z z' cmpl #k 0110 1110 0011 kkkk k-lr 2 2 - z c - - - - - - 32 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 (8) bit manipulation mnemonic object code ( binary ) operation description byte cycle flag czs clm b 1111 00bb ram[hl] b ? 011--1 clp p,b 0110 1101 11bb pppp port[p] b ? 022--1 clpl 0110 0000 port[lr 3-2 +4] lr 1-0 ? 012--1 clr y,b 0110 1100 11bb yyyy ram[y] b ? 022--1 sem b 1111 01bb ram[hl] b ? 111--1 sep p,b 0110 1101 01bb pppp port[p] b ? 122--1 sepl 0110 0010 port[lr 3-2 +4] lr l-0 ? 112 --1 set y,b 0110 1100 01bb yyyy ram[y] b ? 122--1 tf y,b 0110 1100 00bb yyyy sf ? ram[y] b '22--* tfa b 1111 10bb sf ? acc b '11--* tfm b 1111 11bb sf ? ram[hl] b '11--* tfp p,b 0110 1101 00bb pppp sf ? port[p] b '22--* tfpl 0110 0001 sf ? port[lr 3-2 +4] lr 1-0 '12--* tt y,b 0110 1100 10bb yyyy sf ? ram[y] b 22--* ttp p,b 0110 1101 10bb pppp sf ? port[p] b 22--* (9) subroutine mnemonic object code ( binary ) operation description byte cycle flag czs lcall a 0100 0aaa aaaa aaaa stack[sp] ? pc, 2 2 - - - sp ? sp -1, pc ? a scall a 1110 nnnn stack[sp] ? pc, 1 2 - - - sp ? sp - 1, pc ? a, a = 8n +6 (n=1~15),0086h (n =0) ret 0100 1111 sp ? sp + 1, pc ? stack[sp] 1 2 - - - (10) input/output mnemonic object code ( binary ) operation description byte cycle flag czs ina p 0110 1111 0100 pppp acc ? port[p] 2 2 - z z' inm p 0110 1111 1100 pppp ram[hl] ? port[p] 2 2 - - z' out #k,p 0100 1010 kkkk pppp port[p] ? k22--1 outa p 0110 1111 000p pppp port[p] ? acc 2 2 - - 1 outm p 0110 1111 100p pppp port[p] ? ram[hl] 2 2 - - 1 (11) flag manipulation mnemonic object code ( binary ) operation description byte cycle flag czs cgf 0101 0111 gf ? 011--1 sgf 0101 0101 gf ? 111--1 tfcfc 0101 0011 sf ? cf', cf ? 0110-* 33 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 tgs 0101 0100 sf ? gf 1 1 - - * ttcfs 0101 0010 sf ? cf, cf ? 1111-* tzs 0101 1011 sf ? zf 1 1 - - * (12) interrupt control mnemonic object code ( binary ) operation description byte cycle flag czs cil r 0110 0011 11rr rrrr il ? il & r 2 2 - - 1 dicil r 0110 0011 10rr rrrr eif ? 0,il ? il&r 2 2 - - 1 eicil r 0110 0011 01rr rrrr eif ? 1,il ? il&r 2 2 - - 1 exae 0111 0101 mask ? acc 1 1 - - 1 rti 0100 1101 sp ? sp+1,flag.pc 1 2 * * * ? stack[sp],eif ?1 (13) cpu control mnemonic object code ( binary ) operation description byte cycle flag czs nop 0101 0110 no operation 1 1 - - - (14) timer/counter & data pointer & stack pointer control mnemonic object code ( binary ) operation description byte cycle flag czs ldadpl 0110 1010 1111 1100 acc ? [dp] l 22-z1 ldadpm 0101 0110 1111 1101 acc ? [dp] m 22-z1 ldadph 0101 0110 1111 1110 acc ? [dp] h 22-z1 ldasp 0101 0110 1111 1111 acc ? sp 2 2 - z 1 ldatal 0110 1010 1111 0100 acc ? [ta] l 22-z1 ldatam 0101 0110 1111 0101 acc ? [ta] m 22-z1 ldatah 0101 0110 1111 0110 acc ? [ta] h 22 -z1 ldatbl 0110 1010 1111 1000 acc ? [tb] l 22-z1 ldatbm 0101 0110 1111 1001 acc ? [tb] m 22-z1 ldatbh 0101 0110 1111 1010 acc ? [tb] h 22-z1 stadpl 0110 1001 1111 1100 [dp] l ? acc 2 2 - - 1 stadpm 0110 1001 1111 1101 [dp] m ? acc 2 2 - - 1 stadph 0110 1001 1111 1110 [dp] h ? acc 2 2 - - 1 stasp 0110 1001 1111 1111 sp ? acc 2 2 - - 1 statal 0110 1001 1111 0100 [ta] l ? acc 2 2 - - 1 statam 0110 1001 1111 0101 [ta] m ? acc 2 2 - - 1 statah 0110 1001 1111 0110 [ta] h ? acc 2 2 - - 1 statbl 0110 1001 1111 1000 [ tb] l ? acc 2 2 - - 1 statbm 0110 1001 1111 1001 [tb] m ? acc 2 2 - - 1 statbh 0110 1001 1111 1010 [tb] h ? acc 2 2 - - 1 34 * this specification are subject to be changed without notice. EM73461 4-bit micro-controller for lcd product 7.1.1998 **** symbol description symbol description symbol description hr h register lr l register pc program counter dp data pointer sp stack pointer stack[sp] stack specified by sp a cc accumulator flag all flags cf carry flag zf zero flag sf status flag gf general flag ei enable interrupt register il interrupt latch mask interrupt mask port[p] port ( address : p ) ta timer/counter a tb timer/counter b ram[hl] data memory (address : hl ) ram[x] data memory (address : x ) rom[dp] l low 4-bit of program memory rom[dp] h high 4-bit of program memory [dp] l low 4-bit of data pointer register [dp] m middle 4-bit of data pointer register [dp] h high 4-bit of data pointer register [ta] l ([tb] l ) low 4-bit of timer/counter a (timer/counter b) register [ta] m ([tb] m ) middle 4-bit of timer/counter a [ta] h ([tb] h ) high 4-bit of timer/counter a (timer/counter b) register (timer/counter b) register ? transfer ? exchange + addition - substraction & logic and logic or ^ logic xor ' inverse operation . concatenation #k 4-bit immediate data x 8-bit ram address y 4-bit zero-page address p 4-bit or 5-bit port address b bit address r 6-bit interrupt latch pc 11-6 bit 11 to 6 of program counter lr 1 -0 contents of bit assigned by bit a 5-0 bit 5 to 0 of destination address for 1 to 0 of lr branch instruction lr 3-2 bit 3 to 2 of lr - - |
Price & Availability of EM73461
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |